View IS42VM32800D_8487578.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

integrated silicon solution, inc . - www.issi.com 1 rev. a 04/11/2012 copyright ? 2010 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time with- out notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the latest version of this device specifcation before relying on any published information and before placing orders for products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to signifcantly affect its safety or effectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances is42vm83200d / is42vm16160d / IS42VM32800D 32mx8, 16mx16, 8mx32 256mb mobile synchronous dram april 2012 features ? fully synchronous; all signals referenced to a positive clock edge ? internal bank for hiding row access and pre- charge ? programmable cas latency: 2, 3 ? programmable burst length: 1, 2, 4, 8, and full page ? programmable burst sequence: ? sequential and interleave ? auto refresh (cbr) ? tcsr (temperature compensated self refresh) ? pasr (partial arrays self refresh): 1/16, 1/8, 1/4, 1/2, and full ? deep power down mode (dpd) ? driver strength control (ds): 1/4, 1/2, and full options ? confgurations: C 32m x 8 C 16m x 16 C 8m x 32 ? power supply is42vmxxx C v dd /v ddq = 1.8v ? packages: x8 Ctsop ii (54) x16 Ctsop ii (54), bga (54) x32 C tsop ii (86), bga (90) ? temperature range: commercial (0c to +70c) industrial (C40 oc to 85 oc) parameter 32m x 8 16m x 16 8m x 32 confguration 8m x 8 x 4 banks 4m x 16 x 4 banks 2m x 32 x 4 banks refresh count 8k/64ms 8k/64ms 4k/64ms row addressing a0-a12 a0-a12 a0-a11 column addressing a0-a9 a0-a8 a0-a8 bank addressing ba0, ba1 ba0, ba1 ba0, ba1 precharge addressing a10 a10 a10 addressing table description issi's 256mb mobile synchronous dram achieves high- speed data transfer using pipeline architecture. all input and output signals refer to the rising edge of the clock input. both write and read accesses to the sdram are burst oriented. the 256mb mobile synchronous dram is designed to minimize current consumption making it ideal for low-power applications. both tsop and bga packages are offered, including industrial grade products. parameter -8 (1) -12 (2) unit clk cycle time cas latency = 3 8 12 ns cas latency = 2 10 - ns clk frequency cas latency = 3 125 83 mhz cas latency = 2 100 - mhz access time from clk cas latency = 3 6 10 ns cas latency = 2 9 - ns key timing parameters notes: 1. available for x8/x16 only 2. available for x32 only
2 integrated silicon solution, inc . - www.issi.com rev. a 04/11/2012 is42vm83200d / is42vm16160d / IS42VM32800D general description issis 256mb sdram is a high speed cmos, dynamic random-access memory designed to operate in 1.8v v dd / v ddq memory systems containing 268,435,456 bits. internally confgured as a quad-bank dram with a synchronous interface. the 256mb sdram includes an auto refresh mode, and a power-saving, power-down mode. all signals are registered on the positive edge of the clock signal, clk. all inputs and outputs are lvcmos (vdd = 1.8v) compatible. the 256mb sdram has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access. a self-timed row precharge initiated at the end of the burst sequence is available with the auto precharge function enabled. precharge one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. sdram read and write accesses are burst oriented starting at a selected location and continuing for a programmed number of locations in a programmed sequence. the registration of an active command begins accesses, followed by a read or write command. the active command in conjunction with address bits registered are used to select the bank and row to be accessed (ba0, ba1 select the bank; a0-a12 (x8 and x16) and a0-a11 (x32) select the row). the read or write commands in conjunction with address bits registered are used to select the starting column location for the burst access. programmable read or write burst lengths consist of 1, 2, 4 and 8 locations, or full page, with a burst terminate option. clk cke cs ras cas we a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ba0 ba1 a10 a12 command decoder & clock genera to r mode register refresh contr oller refresh counter self refresh cont roller ro w address la tch mul tiplexer column address la tch burst counter column address buffer column decoder da ta in buffer da ta out buffer dqml dqmh dq 0-15 v dd /v ddq v ss /v ss q 13 13 9 13 13 9 16 16 16 16 512 (x 16) 8192 8192 8192 ro w decoder 8192 memor y cell arra y ba nk 0 sense amp i/o ga te bank contr ol logic ro w address buffer a11 2 functional block diagram ( for 16m x 16 b anks shown)
integrated silicon solution, inc . - www.issi.com 3 rev. a 04/11/2012 is42vm83200d / is42vm16160d / IS42VM32800D pin configurations 54 pin tsop C type ii for x8 v dd dq0 v dd q nc dq1 v ss q nc dq2 v dd q nc dq3 v ss q nc v dd nc we cas ras cs ba0 ba1 a10 a0 a1 a2 a3 v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 v ss dq7 v ss q nc dq6 v dd q nc dq5 v ss q nc dq4 v dd q nc v ss nc dqm clk cke a12 a11 a9 a8 a7 a6 a5 a4 v ss pin descriptions 32m x 8 pin name a0Ca12 row address input a0Ca9 column address input ba0, ba1 bank select address dq0Cdq7 data input/output clk system clock input cke clock enable cs chip select ras row address strobe command 32m x 8 pin name cas column address strobe command we write enable dqm data input/output mask vdd power vss ground vddq power supply for i/o pin vssq ground for i/o pin nc no connection
4 integrated silicon solution, inc . - www.issi.com rev. a 04/11/2012 is42vm83200d / is42vm16160d / IS42VM32800D pin configurations 54 pin tsop C type ii for x16 16m x16 pin name a0Ca12 row address input a0Ca8 column address input ba0, ba1 bank select address dq0Cdq15 data input/output clk system clock input cke clock enable cs chip select ras row address strobe command cas column address strobe command pin descriptions 16m x16 pin name we write enable dqml / dqmh data input/output mask vdd power vss ground vddq power supply for i/o pin vssq ground for i/o pin nc no connection v dd dq0 v dd q dq1 dq2 v ss q dq3 dq4 v dd q dq5 dq6 v ss q dq7 v dd dqml we cas ras cs ba0 ba1 a10 a0 a1 a2 a3 v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 v ss dq15 v ss q dq14 dq13 v dd q dq12 dq11 v ss q dq10 dq9 v dd q dq8 v ss nc dqmh clk cke a12 a11 a9 a8 a7 a6 a5 a4 v ss
integrated silicon solution, inc . - www.issi.com 5 rev. a 04/11/2012 is42vm83200d / is42vm16160d / IS42VM32800D pin configurations 54-ball fbga for x16 (top view) (8.00mm x 13.00mm body, 0.8mm ball pitch) pin descriptions 16m x16 pin name a0Ca12 row address input a0Ca8 column address input ba0, ba1 bank select address dq0Cdq15 data input/output clk system clock input cke clock enable cs chip select ras row address strobe command 16m x16 pin name cas column address strobe command we write enable dqml / dqmh data input/output mask vdd power vss ground vddq power supply for i/o pin vssq ground for i/o pin nc no connection 1 2 3 4 5 6 7 8 9 a b c d e f g h j vss dq14 dq12 dq10 dq8 dqmh a12 a8 vss dq15 dq13 dq11 dq9 nc clk a11 a7 a5 vssq vddq vssq vddq vss cke a9 a6 a4 vddq vssq vddq vssq vdd cas ba0 a0 a3 dq0 dq2 dq4 dq6 dqml ras ba1 a1 a2 vdd dq1 dq3 dq5 dq7 we cs a10 vdd
6 integrated silicon solution, inc . - www.issi.com rev. a 04/11/2012 is42vm83200d / is42vm16160d / IS42VM32800D pin configurations 86 pin tsop C type ii for x32 8m x32 pin name a0Ca11 row address input a0Ca8 column address input ba0, ba1 bank select address dq0Cdq31 data input/output clk system clock input cke clock enable cs chip select ras row address strobe command cas column address strobe command pin descriptions 8m x32 pin name we write enable dqm0 - dqm3 data input/output mask vdd power vss ground vddq power supply for i/o pin vssq ground for i/o pin nc no connection v dd dq0 v dd q dq1 dq2 v ss q dq3 dq4 v dd q dq5 dq6 v ss q dq7 nc v dd dqm0 we cas ras cs a11 ba0 ba1 a10 a0 a1 a2 dqm2 v dd nc dq16 v ss q dq17 dq18 v dd q dq19 dq20 v ss q dq21 dq22 v dd q dq23 v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 v ss dq15 v ss q dq14 dq13 v dd q dq12 dq11 v ss q dq10 dq9 v dd q dq8 nc v ss dqm1 nc nc clk cke a9 a8 a7 a6 a5 a4 a3 dqm3 v ss nc dq31 v dd q dq30 dq29 v ss q dq28 dq27 v dd q dq26 dq25 v ss q dq24 v ss
integrated silicon solution, inc . - www.issi.com 7 rev. a 04/11/2012 is42vm83200d / is42vm16160d / IS42VM32800D pin configurations 90-ball fbga for x32 (top view) (8.00mm x 13.00mm body, 0.8mm ball pitch) 1 2 3 4 5 6 7 8 9 a b c d e f g h j k l m n p r dq26 dq28 vssq vssq vddq vs s a4 a7 clk dqm1 vddq vssq vssq dq11 dq13 dq24 vddq dq27 dq29 dq31 dqm3 a5 a8 cke nc dq8 dq10 dq12 vddq dq15 vs s vssq dq25 dq30 nc a3 a6 nc a9 nc vs s dq9 dq14 vssq vs s vdd vddq dq22 dq17 nc a2 a10 nc ba 0 cas vdd dq6 dq1 vddq vdd dq23 vssq dq20 dq18 dq16 dqm2 a0 ba 1 cs we dq7 dq5 dq3 vssq dq0 dq21 dq19 vddq vddq vssq vdd a1 a11 ras dqm0 vssq vddq vddq dq4 dq2 pin descriptions 8m x32 pin name a0Ca11 row address input a0Ca8 column address input ba0, ba1 bank select address dq0Cdq31 data input/output clk system clock input cke clock enable cs chip select ras row address strobe command cas column address strobe command 8m x32 pin name we write enable dqm0 - dqm3 data input/output mask vdd power vss ground vddq power supply for i/o pin vssq ground for i/o pin nc no connection
8 integrated silicon solution, inc . - www.issi.com rev. a 04/11/2012 is42vm83200d / is42vm16160d / IS42VM32800D mobile sdram functionality issis 256mb mobile sdrams are pin compatible and have similar functionality with issis standard sdrams, but offer lower operating voltages and power saving features. for detailed descriptions of pin functions, command truth tables, functional truth tables, device operation as well as timing diagrams please refer to issi document mobile synchronous dram device operations & timing diagrams listed at www.issi.com register definition mode register (mr) & extended mode register (emr) there are two mode registers in the mobile sdram; mode register (mr) and extended mode register (emr). the mode register is discussed below, followed by the extended mode register. the mode register is used to defne the specifc mode of operation of the sdram. this defnition includes the selection of burst length, a burst type, cas latency, operating mode, and a write burst mode. the mode register is programmed via the load mode register command and will retain the stored information until it is programmed again or the device loses power. the emr controls the functions beyond those controlled by the mr. these additional functions are special features of the mobile sdram. they include temperature-compensated self refresh (tcsr) control, partial-array self refresh (pasr), and output drive strength. the emr is programmed via the mode register set command with ba1 = 1 and ba0 = 0 and retains the stored information until it is programmed again or the device loses power. not programming the extended mode register upon initialization will result in default settings for the low-power features. the extended mode will default with the temperature sensor enabled, full drive strength, and full array (all 4 banks) refresh. mode register defnition the mr is used to defne the specifc mode of operation of the sdram. this defnition includes the selection of a burst length, a burst type, a cas latency, an operating mode and a write burst mode, as shown in figure mode register definition. the mode register is programmed via the load mode register command and will retain the stored information until it is programmed again or the device loses power. mode register bits m0 - m2 specify the burst length, m3 specifes the type of burst (sequential or interleaved), m4 - m6 specify the cas latency, m7 and m8 specify the operating mode, m9 specifes the write burst mode, and m10, m11, and m12 are reserved for future use. the mode register must be loaded when all banks are idle, and the controller must wait the specifed time before initiating the subsequent operation. violating either of these requirements will result in unspecifed operation.
integrated silicon solution, inc . - www.issi.com 9 rev. a 04/11/2012 is42vm83200d / is42vm16160d / IS42VM32800D burst length read and write accesses to the sdram are burst oriented, with the burst length being programmable, as shown in mode register definition. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 1, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. the full-page burst is used in conjunction with the burst terminate command to generate arbitrary burst lengths. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a1-a8 (x32), a1-a8 (x16) or a1-a9 (x8) when the burst length is set to two; by a2-a8 (x32), a2-a8 (x16) or a2-a9 (x8) when the burst length is set to four; and by a3-a8 (x32), a3-a8 (x16) or a3-a9 (x8) when the burst length is set to eight. the remaining (least signifcant) address bit(s) are used to select the starting location within the block. full-page bursts wrap within the page if the boundary is reached. mode register definition latency mode m6 m5 m4 cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 2 0 1 1 3 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved 1. note: a12 x8 and x16, a11 x32 2. to ensure compatibility with future devices, should program a12, a11, a10 = "0" write burst mode m9 mode 0 programmed burst length 1 single location access operating mode m8 m7 m6-m0 mode 0 0 defined standard operation all other states reserved burst type m3 type 0 sequential 1 interleaved b urst lengt h m2 m1 m0 m3=0 m3=1 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 full page reserved reserved address bus (ax) mode register (mx) (1) ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ba1 ba0 mode register definition 0 0 program mode register 0 1 reserved 1 0 program extended mode register 1 1 reserved
10 integrated silicon solution, inc . - www.issi.com rev. a 04/11/2012 is42vm83200d / is42vm16160d / IS42VM32800D burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in burst definition table. b urst definition burst starting column order of accesses within a burst length address type = sequential type = interleaved a 0 2 0 0-1 0-1 1 1-0 1-0 a 1 a 0 0 0 0-1-2-3 0-1-2-3 4 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 a 2 a 1 a 0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full n = a0-a8 (x16, x32) cn, cn + 1, cn + 2 not supported page n = a0-a9 (x8) cn + 3, cn + 4... (y) (location 0-y) cn - 1, cn cas latency the cas latency is the delay, in clock cycles, between the registration of a read command and the availability of the frst piece of output data. the latency can be set to two or three clocks. if a read command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. the dqs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. for example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at t0 and the latency is programmed to two clocks, the dqs will start driving after t1 and the data will be valid by t2, as shown in cas latency diagrams. reserved states should not be used as unknown operation or incompatibility with future versions may result. operating mode the normal operating mode is selected by setting m7 and m8 to zero; the other combinations of values for m7 and m8 are reserved for future use and/or test modes. the programmed burst length applies to both read and write bursts.
integrated silicon solution, inc . - www.issi.com 11 rev. a 04/11/2012 is42vm83200d / is42vm16160d / IS42VM32800D test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. write burst mode when m9 = 0, the burst length programmed via m0-m2 applies to both read and write bursts; when m9 = 1, the programmed burst length applies to read bursts, but write accesses are single-location (nonburst) accesses. don't care undefined clk command dq read nop nop nop cas latency - 3 t ac t oh d out t0 t1 t2 t3 t4 t lz clk command dq read nop nop cas latency - 2 t ac t oh d out t0 t1 t2 t3 t lz cas l atency
12 integrated silicon solution, inc . - www.issi.com rev. a 04/11/2012 is42vm83200d / is42vm16160d / IS42VM32800D extended mode register definition the extended mode register is programmed via the mode register set command (ba1 = 1, ba0 = 0) and retains the stored information until it is programmed again or the device loses power. the extended mode register must be programmed with e7 through e11 (or e12 for x8 & x16) set to 0. the extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specifed time before initiating any subsequent operation. violating either of these requirements results in unspecifed operation. the extended mode register must be programmed to ensure proper operation. temperature-compensated self refresh (tcsr) tcsr allows the controller to program the refresh interval during self refresh mode, according to the case temperature of the mobile device. this allows great power savings during self refresh during most operating temperature ranges. only during extreme temperatures would the controller have to select a higher tcsr level that will guarantee data during self refresh. ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 pasr e2 e1 e0 partial array self refresh coverage 0 0 0 fully array (4 banks) - (default) 0 0 1 half array (banks 0, 1) 0 1 0 quarter array (bank 0) 0 1 1 reserved 1 0 0 reserved 1 0 1 one-eighth array (1/2 bank 0) 1 1 0 one-sixteenth array (1/4 bank 0) 1 1 1 reserved tcsr e4 e3 max. case temp. 0 0 70 o c 0 1 45 o c 1 0 15 o c 1 1 85 o c (default) ds e6 e5 driver strength 0 0 full strength driver (default) 0 1 half strength driver 1 0 quarter strength driver 1 1 reserved set to "0" e12 e11 e10 e9 e8 e7 e6-e0 0 0 0 0 0 0 valid normal operation C C C C C C C all other states reserved ba1 ba0 mode register defnition 0 0 program mode register 0 1 reserved 1 0 program extended mode register 1 1 reserved address bus (ax) ext. mode reg. (ex) note: a12 x8 and x16, a11 x32
integrated silicon solution, inc . - www.issi.com 13 rev. a 04/11/2012 is42vm83200d / is42vm16160d / IS42VM32800D every cell in the dram requires refreshing due to the capacitor losing its charge over time. the refresh rate is dependent on temperature. at higher temperatures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed more often. historically, during self refresh, the refresh rate has been set to accommodate the worst case, or highest temperature range, expected. thus, during ambient temperatures, the power consumed during refresh was unnecessarily high because the refresh rate was set to accommodate the higher temperatures. setting e4 and e3 allows the dram to accommodate more specifc temperature regions during self refresh. the default for issi 256mb mobile sdram is tcsr = 85c to guarantee refresh operation. this mode of operation has a higher current consumption because the self refresh oscillator is set to refresh the sdram cells more often than needed. by using an external temperature sensor to determine the operating temperature the mobile sdram can be programmed for lower temperature and refresh rates, effectively reducing current consumption by a signifcant amount. there are four temperature settings, which will vary the self refresh current according to the selected temperature. this selectable refresh rate will save power when the mobile dram is operating at normal temperatures. partial-array self refresh (pasr) for further power savings during self refresh, the pasr feature allows the controller to select the amount of memory that will be refreshed during self refresh. the refresh options are all banks (banks 0, 1, 2, and 3); two banks (banks 0 and 1); and one bank (bank 0). in addition partial amounts of bank 0 (half or quarter of the bank) may be selected. write and read commands occur to any bank selected during standard operation, but only the selected banks in pasr will be refreshed during self refresh. its important to note that data in banks 2 and 3 will be lost when the two- bank option is used. data will be lost in banks 1, 2, and 3 when the one-bank option is used. driver strength (ds) bits e5 and e6 of the emr can be used to select the driver strength of the dq outputs. this value should be set according to the applications requirements. the default is full driver strength. deep power down (dpd) deep power down mode is for maximum power savings and is achieved by shutting down power to the entire memory array of the mobile device. data will be lost once deep power down mode is executed. dpd mode is entered by having all banks idle, cs and we held low, with ras and cas high at the rising edge of the clock, while cke is low. cke must be held low during dpd mode. to exit dpd mode, cke must be asserted high. upon exit from dpd mode, at least 200ms of valid clocks with either nop or command inhibit commands are applied to the command bus, followed by a full mobile sdram initialization sequence, is required.
14 integrated silicon solution, inc . - www.issi.com rev. a 04/11/2012 is42vm83200d / is42vm16160d / IS42VM32800D absolute max imum ratings (1) symbol parameters rating unit v dd max maximum supply voltage C0.35 to +2.8 v v ddq max maximum supply voltage for output buffer C0.35 to +2.8 v v in input voltage C0.35 to v ddq + 0.5 v v out output voltage C0.35 to v ddq + 0.5 v p d max allowable power dissipation 1 w i cs o utput shorted current 50 ma t opr o perating temperature com. 0 to +70 c ind. C40 to +85 c t stg storage temperature C65 to +150 c notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. all voltages are referenced to vss. electrical s pecifications dc recommended operating conditions is42vmxxx - 1.8v operation symbol parameters min. typ. max. unit v dd supply voltage 1.7 1.8 1.95 v v ddq i/o supply voltage 1.7 1.8 1.95 v v ih (1) input high voltage 0.8xv ddq C v ddq +0.3 v v il (2) input low voltage -0.3 C 0.8 v i il input leakage current (0v v in v dd ) -1 C +1 a i ol output leakage current (output disabled, 0v v out v dd ) -1.5 C +1.5 a v oh output high voltage current (i oh = -100ma) 0.9xv ddq C C v v ol output low voltage current (i ol = 100ma) C C 0.2 v notes: 1. v ih (overshoot): v ih (max) = v ddq +1.2v (pulse width < 3ns). 2. v il (undershoot): v ih (min) = -1.2v (pulse width < 3ns). 3. all voltages are referenced to vss. symbol parameters min. max. unit c in 1 input capacitance: clk 2.5 3.5 pf c in 2 input capacitance: all other input pins 2.5 3.8 pf c i / o data input/output capacitance: i/os 4.0 6.0 pf c apacitance c haracteristics - x8, x16 symbol parameters min. max. unit c in 1 input capacitance: clk 2.5 3.5 pf c in 2 input capacitance: all other input pins 2.5 3.8 pf c i / o data input/output capacitance: i/os 4.0 6.5 pf c apacitance c haracteristics - x32
integrated silicon solution, inc . - www.issi.com 15 rev. a 04/11/2012 is42vm83200d / is42vm16160d / IS42VM32800D symbol parameter test condition C8 unit i dd 1 (1) operating current one bank active, cl = 3, bl = 2, tclk = tclk(min), trc = trc(min) 90 ma i dd 2 p (4) precharge standby current (in power-down mode) cke v il (max), tck = 15ns cs v dd - 0.2v 1 ma i dd 2 ps (4) precharge standby current with clock stop (in power-down mode) cke v il (max), clk v il (max) cs v dd - 0.2v 1 ma i dd 2 n (2) precharge standby current (in non power-down mode) cs v dd - 0.2v, cke v ih (min) tck = 15 ns 20 ma i dd 2 ns precharge standby current with clock stop (in non-power down mode) cs v dd - 0.2v, cke v ih (min) all inputs stable 7 ma i dd 3 p (2) active standby current (in power-down mode) cke v il (max), cs v dd - 0.2v tck = 15 ns, all banks active 3 ma i dd 3 ps active standby current with clock stop (in power-down mode) cke v il (max), clk v il (max) cs v dd - 0.2v, all banks active 3 ma i dd 3 n (2) active standby current (in non power-down mode) cs v dd - 0.2v, cke v ih (min) tck = 15 ns, all banks active 25 ma i dd 3 ns active standby current with clock stop (in non power-down mode) cs v dd - 0.2v, cke v ih (min) all inputs stable, all banks active 10 ma i dd 4 operating current all banks active, bl = full, cl = 3 tck = tck(min) 115 ma i dd 5 auto-refresh current trc = trc(min), tclk = tclk(min) 130 ma i dd 6 self-refresh current cke 0.2v 1.2 ma i dd 7 self-refresh: cke = low; t ck = t ck (min); address, control, and data bus inputs are stable full array, 85 o c full array, 45 o c half array, 85 o c half array, 45 o c 1/4th array, 85 o c 1/4th array, 45 o c 1/8th array, 85 o c 1/8th array, 45 o c 1/16th array, 85 o c 1/16th array, 45 o c 1200 800 1000 670 800 540 700 470 600 400 a i zz (3,4) deep power down current cke 0.2v 20 a dc electrical characteristics vdd = 1.8v (x8 and x16) notes: 1. i dd (max) is specifed at the output open condition. 2. input signals are changed one time during 30ns. 3. izz values shown are nominal at 25 o c. izz is not tested. 4. tested after 500ms delay
16 integrated silicon solution, inc . - www.issi.com rev. a 04/11/2012 is42vm83200d / is42vm16160d / IS42VM32800D symbol parameter test condition C12 unit i dd 1 (1) operating current one bank active, cl = 3, bl = 2, tclk = tclk(min), trc = trc(min) 90 ma i dd 2 p (4) precharge standby current (in power-down mode) cke v il (max), tck = 15ns cs v dd - 0.2v 1 ma i dd 2 ps (4) precharge standby current with clock stop (in power-down mode) cke v il (max), clk v il (max) cs v dd - 0.2v 1 ma i dd 2 n (2) precharge standby current (in non power-down mode) cs v dd - 0.2v, cke v ih (min) tck = 15 ns 20 ma i dd 2 ns precharge standby current with clock stop (in non-power down mode) cs v dd - 0.2v, cke v ih (min) all inputs stable 7 ma i dd 3 p (2) active standby current (in power-down mode) cke v il (max), cs v dd - 0.2v tck = 15 ns, all banks active 3 ma i dd 3 ps active standby current with clock stop (in power-down mode) cke v il (max), clk v il (max) cs v dd - 0.2v, all banks active 3 ma i dd 3 n (2) active standby current (in non power-down mode) cs v dd - 0.2v, cke v ih (min) tck = 15 ns, all banks active 25 ma i dd 3 ns active standby current with clock stop (in non power-down mode) cs v dd - 0.2v, cke v ih (min) all inputs stable, all banks active 10 ma i dd 4 operating current all banks active, bl = full, cl = 3 tck = tck(min) 90 ma i dd 5 auto-refresh current trc = trc(min), tclk = tclk(min) 165 ma i dd 6 self-refresh current cke 0.2v 1.2 ma i dd 7 self-refresh: cke = low; t ck = t ck (min); address, control, and data bus inputs are stable full array, 85 o c full array, 45 o c half array, 85 o c half array, 45 o c 1/4th array, 85 o c 1/4th array, 45 o c 1/8th array, 85 o c 1/8th array, 45 o c 1/16th array, 85 o c 1/16th array, 45 o c 1200 800 1000 670 800 540 700 470 600 400 a i zz (3,4) deep power down current cke 0.2v 20 a dc electrical characteristics vdd = 1.8v (x32) notes: 1. i dd (max) is specifed at the output open condition. 2. input signals are changed one time during 30ns. 3. izz values shown are nominal at 25 o c. izz is not tested. 4. tested after 500ms delay
integrated silicon solution, inc . - www.issi.com 17 rev. a 04/11/2012 is42vm83200d / is42vm16160d / IS42VM32800D ac electrical characteristics (1, 2, 3) -8 -12 symbol parameter min. max. min. max. unit tck3 tck2 clock cycle time cas latency = 3 cas latency = 2 8 10 C C 12 C C C ns ns tac3 tac2 access time from clk cas latency = 3 cas latency = 2 C C 6 9 C C 10 C ns ns tchi clk high level width 2.5 C 2.5 C ns tcl clk low level width 2.5 C 2.5 C ns toh3 toh2 output data hold time cas latency = 3 cas latency = 2 2.7 2.7 C C 2.7 C C C ns ns tlz output low impedance time 0 C 0 C ns thz3 thz2 output high impedance time cas latency = 3 cas latency = 2 2.7 2.7 6 9 2.7 C 10 C ns tds input data setup time (2) 1.5 C 1.5 C ns tdh input data hold time (2) 1.0 C 1.0 C ns tas address setup time (2) 1.5 C 1.5 C ns tah address hold time (2) 1.0 C 1.0 C ns tcks cke setup time (2) 1.5 C 1.5 C ns tckh cke hold time (2) 1.0 C 1.0 C ns tcs command setup time (cs, ras, cas, we, dqm) (2) 1.5 C 1.5 C ns tch command hold time ((cs, ras, cas, we, dqm) (2) 1.0 C 1.0 C ns trc command period (ref to ref / act to act) 80 C 120 C ns tras command period (act to pre) 56 100k 84 100k ns trp command period (pre to act) 24 C 36 C ns trcd active command to read/ write command delay time 22 C 36 C ns trrd command period (act [0] to act [1]) 16 C 20 C ns tdpl input data to precharge 16 C 20 C ns command delay time tdal input data to active/refresh command delay time (during auto-precharge) 40 C 50 C ns tmrd mode register program time 15 C 20 C ns tdde power down exit setup time 8 C 10 C ns txsr exit self-refresh to active time 80 C 100 C ns tt transition time 0.3 1.2 0.3 1.2 ns tref refresh cycle time 8k times (x8/x16) C C C 64 ms 4k times (x32) C 64 C 64 ms notes: 1. the power-on sequence must be executed before starting memory operation. 2. measured with tt = 1 ns. if clock rising time is longer than 1ns, (tt/2 - 0.5) ns should be added to the parameter. 3. the reference level is 0.9v when measuring input signal timing. rise and fall times are measured between v ih (min.) and v il (max).
18 integrated silicon solution, inc . - www.issi.com rev. a 04/11/2012 is42vm83200d / is42vm16160d / IS42VM32800D operating frequency / latency relationships symbol p arameter -8 -12 units clock cycle time 8 12 ns operating frequency 125 83 mhz t cac cas latency 3 3 cycle t rcd active command to read/write command delay time 3 3 cycle t rac ras latency (t rcd + t cac ) cas latency = 3 6 6 cycle t rc command period (ref to ref / act to act) 10 10 cycle t ras command period (act to pre) 7 7 cycle t rp command period (pre to act) 3 3 cycle t rrd command period (act[0] to act [1]) 2 2 cycle t ccd column command delay time (read, reada, writ, writa) 1 1 cycle t dpl input data to precharge command delay time 2 2 cycle t dal input data to active/refresh command delay time (during auto-precharge) 5 5 cycle t rbd burst stop command to output in high-z delay time (write) cas latency = 3 3 3 cycle t wbd burst stop command to input in invalid delay time (write) 0 0 cycle t rql precharge command to output in high-z delay time (read) cas latency = 3 3 3 cycle t wdl precharge command to input in invalid delay time (write) 0 0 cycle t pql last output to auto-precharge start time (read) cas latency = 3 -2 -2 cycle t qmd dqm to output delay time (read) 2 2 cycle t dmd dqm to input delay time (write) 0 0 cycle t mrd mode register set to command delay time 2 2 cycle
integrated silicon solution, inc . - www.issi.com 19 rev. a 04/11/2012 is42vm83200d / is42vm16160d / IS42VM32800D ordering information C v dd = 1.8v commercial range: (0c to +70c) confguration frequency (mhz) speed (ns) order part no. package 16mx16 125 8 is42vm16160d-8bl 54-ball bga, lead-free 8mx32 83 12 IS42VM32800D-12bl 90-ball bga, lead-free industrial range: (C40oc to 85oc) note: contact issi for leaded parts support. confguration frequency (mhz) speed (ns) order part no. package 32mx8 125 8 is42vm83200d-8tli 54-pin tsop ii, lead-free 16mx16 125 8 is42vm16160d-8tli 54-pin tsop ii, lead-free is42vm16160d-8bli 54-ball bga, lead-free 8mx32 83 12 IS42VM32800D-12tli 86-pin tsop ii, lead-free IS42VM32800D-12bli 90-ball bga, lead-free
20 integrated silicon solution, inc . - www.issi.com rev. a 04/11/2012 is42vm83200d / is42vm16160d / IS42VM32800D
integrated silicon solution, inc . - www.issi.com 21 rev. a 04/11/2012 is42vm83200d / is42vm16160d / IS42VM32800D 1. controlling dimension : mm . 2. reference document : jedec ms-207 note : package outline 08/29/2008
22 integrated silicon solution, inc . - www.issi.com rev. a 04/11/2012 is42vm83200d / is42vm16160d / IS42VM32800D note : 4. formed leads shall be planar with respect to one another within 0.1mm 2. dimension d and e1 do not include mold protrusion . at the seating plane after final test. 1. controlling dimension : mm 3. dimension b does not include dambar protrusion/intrusion. 09/26/2006 package outline
integrated silicon solution, inc . - www.issi.com 23 rev. a 04/11/2012 is42vm83200d / is42vm16160d / IS42VM32800D 0.45 0.80 d 1 2. reference document : jedec mo-207 1. controlling dimension : mm . note : package outline 08/14/2008

▲Up To Search▲

Price & Availability of IS42VM32800D

	To Download IS42VM32800D Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .